Examples of conventional electron emitting devices of the type to which the present invention relates are disclosed in U.S. Pat. Nos. 3,755,704; 3,812,559; 4,857,161; 4,940,916; 5,194,780 and 5,225,820. The disclosures of those patents are incorporated herein by reference.
Microtip emission cathode structures usable in FED field emission flat-panel image display devices, as described in the referenced patents, typically comprise thin film metal/insulator/metal sandwich structures deposited on a glass or silicon support substrate. In a usual self-aligning method of fabrication, first and second conductive layers are deposited on the substrate, separated by an intervening dielectric insulating layer which functions to space and insulate the conductive layers. The bottom conductive layer functions as the emitting or cathode electrode. The top conductive layer functions as the extractor or gate electrode. Apertures are formed in the top conducting layer and in the intervening dielectric material, and a microtip emitter (sometimes called an electron field emitting spike, needle or protuberance) is formed within each aperture in electrical communication with the bottom conductive layer. Traditional designs have placed the emitters in either random or rectangular matrix arrays.
Early implementations formed the microtips directly on the lower or cathode electrode. Such arrangements, however, provided little protection against excessive current draw. The use of a resistive layer was therefore proposed to provide a ballast against excessive current in each microtip emitter, and consequently to homogenize the electron emission. The Borel, et al. '916 patent describes the use of a resistive layer above the cathode electrode and beneath the microtips. Such vertical resistor approach helps eliminate nonuniformity caused by excessively bright spots and reduces breakdown risk at the microtips by limiting current flow when local short-circuiting occurs between individual microtips and the gate. Under the Borel approach, however, when a short circuit occurs between a microtip and the gate, the full voltage applied between the gate and cathode conductors is applied vertically across the resistive coating. This requires the resistive coating to be thick enough to withstand the full gate-to-cathode voltage without breaking down due to heat. Thus, the existence of "pinhole" or other defects which locally reduce thickness of the resistive layer will lead to breakdown.
The Meyer '780 patent overcomes this deficiency by use of a lateral resistor cathode structure for a field emission device. A plurality of arrays of electrically conductive microtips are formed on a resistive layer, within respective mesh spacings of a conductive layer which is patterned into a mesh structure configuration. This arrangement provides an improvement in breakdown resistance of a field effective emissive device, without requiring increasing the thickness of the resistive layer. The mesh-like structure of the cathode conductor (and/or the gate conductor), permits the cathode conductor and the resistive coating to lie substantially in the same plane. In such configuration, the breakdown resistance is no longer susceptible to defects in the vertical thickness of the resistive coating, because it is the lateral separation of the microtips from the cathode conductor by the resistive coating which provides the ballast against excessive current. It is therefore, sufficient to maintain a horizontal distance between the cathode conductor and the microtip which is adequate to prevent breakdown, while still retaining a homogenization affect for which the resistive coating is supplied.
In both the '916 and '780 approaches, the ballast is in the form of a resistive voltage drop, such that those microtips drawing the most current have the greatest resistive drop, thus acting in such a way as to limit microtip current. An equivalent circuit of the '916 or '780 ballast arrangement would have each tip in series with an individual buffer resistor to limit the field emission current. However, the ballast resistance between the microtips and the cathode conductor varies with the position of the individual microtip within the array. In a four-by-four rectangular matrix array, for example, a microtip in the corner of the array has a lower ballast resistance than a microtip at the side of the array, and a microtip in the side has a lower ballast resistance than a microtip in the interior.
The difference in ballast resistance among microtips becomes even more pronounced as the size of the array or the spacing between microtips increases. There is, therefore, a need for microtip emission cathode structures, and displays incorporating such structures, having all microtips in the same array at substantially equal potential.
An FED (field emission device) flat-panel image display device of the type described in Meyer U.S. Pat. No. 5,194,780 is shown in FIGS. 1-4. Such device includes an electron emitter plate 10 spaced across a vacuum gap from an anode plate 11 (FIG. 1). Emitter plate 10 comprises a cathode electrode having a plurality of cellular rectangular arrays 12 of electrically conductive microtips 14 formed on a resistive layer 15, within respective rectangular mesh spacings 16 (FIG. 2) of rectangular grid mesh structure 18, patterned in stripes 19 (referred to as "columns") (FIG. 4) on an upper surface of an electrically insulating (typically glass) substrate 20 overlaid with a thin silicon dioxide (SiO.sub.9 ) film 21. An extraction (or gate) electrode 22 (FIGS. 1 and 2) comprises an electrically conductive layer of cross-stripes 24 (referred to as "rows") (FIG. 4) deposited on an insulating dielectric layer 25 which serves to insulate electrode 22 and space it from the resistive and conductive layers 15, 18. Microtips 14 are in the shape of cones which are formed within apertures 26 through conductive layer 22 and concentric cavities 41 of insulating layer 25. The microtips 14 are formed utilizing a variation of the self-alignment microtip formation technique described in U.S. Pat. No. 3,755,704, wherein apertures 26 and cavities 41 are etched after deposition of layers 22, 25 and wherein a respective microtip 14 is formed within each aperture 26 and cavity 41. The relative parameters of microtips 14, insulating layer 25 and conductive layer 22 are chosen to place the apex of each microtip 14 generally at the level of layer 22 (FIG. 1). Electrode 22 is patterned to form rectangular aperture islands or pads 27 centrally of the mesh spacings 16 in the vicinity of microtip arrays 12, and to remove cross-shaped areas 28 (FIG. 2) over the intersecting conductive strips which form the mesh structure of conductor 18. Bridging strips 29 of electrode 22 are left for electrically interconnecting pads 27 of the same row cross-stripe 24.
Anode plate 11 (FIG. 1) comprises an electrically conductive layer of material 31 deposited on a transparent insulating (typically glass) substrate 32, which is positioned facing extraction electrode 22. The conductive layer 31 is deposited on an inside surface 33 of substrate 32, directly facing gate electrode 22. Conductive layer 31 is typically a transparent conductive material, such as indium-tin oxide (ITO). Anode plate 11 also comprises a coating of phosphor cathodoluminescent material 34, deposited over the conductive layer 31, so as to be directly facing and immediately adjacent extraction electrode 22. In accordance with conventional teachings, groupings of the microtip cellular arrays 12 in mesh spacings 16 corresponding to a particular column-row image pixel location can be energized by applying a negative potential to a selected column stripe 19 (FIG. 4) of cathode mesh structure 18 relative to a selected row cross-stripe 24 of extraction electrode 22, via a voltage source 35, thereby inducing an electric field which draws electrons from the associated subpixel rectangular arrays of microtips 14. The freed electrons are accelerated toward the anode plate 11 which is positively biased by a substantially larger positive voltage applied relative to extraction electrode 22, via the same or a different voltage source 35. Energy from the electrons emitted by the energized microtips 14 and attracted to the anode electrode 31 is transferred to particles of the phosphor coating 34, resulting in luminescence. Electron charge is transferred from phosphor coating 34 to conductive layer 28, completing the electrical circuit to voltage source 35.
As can be seen in FIG. 3, the ballast resistance between microtips 14 and cathode mesh structure 18 varies with the position of the individual microtip 14 within the array 12. In the illustrated four-by-four array 12, for example, there are three "classes" of emitters 14, with different resistive paths R1, R2, R3 to the conductive grid 18 through the resistive layer 15. Microtips 14c in the corners of array 12 will have a lower ballast resistance than microtips 14s located at the external sides of array 12. Microtips 14i located in the interior will have the highest ballast resistance. The effect of the difference in ballast resistance among microtips 14 becomes even more pronounced as the size of the array increases to the point where, in a five-by-five or a six-by-six array, the potential at one or more of the innermost microtips may insufficiently support electron emission. Thus, an arrangement is desired which will enable all microtips 14 to be at a substantially equal potential.